Electronic equipments involving semiconductor devices are indispensable from our daily life. With the advancement of electronic technology, electronic equipments and thus the semiconductor devices inside the electronic equipments are getting smaller and smaller in size, while increasing in functionality. The ever decreasing in size of the semiconductor devices and the ever increasing in functionality have to accomplish a signal routing in a small area of the semiconductor devices.
A fan in wafer level packaging (WLP) technology have been gaining in popularity and is widely applied. This technology provides a wafer level manufacturing of the semiconductor devices with high functions and performances while the size of the semiconductor devices is minimized. There are different kinds of operations in the fan in wafer level packaging technology for signal routing numbers of input/output (I/O) within a small area of the semiconductor device, such as fabrication of fine line circuitries, a reduction in the spaces between the lines, piercing of numbers of trenches or vias through several adjacent layers for electrical interconnection, etc.
However, manufacturing of the electrical interconnection structure in such a small and dense area of the semiconductor device is complicated, because it involves numerous of manufacturing operations and those operations are applied on the small semiconductor device including many different kinds of materials with different properties. The difference on materials would increase a complexity of the manufacturing and yield loss of the semiconductor device, such as poor bondability between components, poor reliability of the vias, cracking or delamination of the electrical interconnection structure, etc. As such, there is a continuous need to improve the electrical interconnection structure and the method for manufacturing the electrical interconnection structure and solve the above deficiencies.